5G NR LDPC Decoder IP Core
High throughput efficiency LDPC decoder for 5G NR
Scalable architecture enabling information rates up to 5.19 Gbps in FPGA implementation. Flexibility to support a broad range of codes from Quasi-Cyclic LDPC family. Available for ASIC and FPGA implementation.
Tannera’s novel 5G NR LDPC implementation provides the highest throughput & hardware resource utilization efficiency available on the market today.
Implementation & performance results for Xilinx Ultrascale+ FPGA:
| Clock | LUTs | FFs | BRAMs | Peak Throughput @ 8 iterations |
Peak Efficiency @ 8 iterations |
|---|---|---|---|---|---|
| 425 MHz | 75,124 | 67,697 | 120.5 | 5.5 Gbps | 73.35 Mbps/kLUT |