5G NR LDPC Encoder IP Core

PRODUCTS >> FEC & DSP IP cores >> 5G NR FEC IP cores

5G NR LDPC Encoder IP Core

High-speed, resource and energy efficient LDPC encoding solution providing up to 40 Gbps per single core.

Tannera’s 5G NR LDPC Encoder IP Core encodes the information bit sequences at the communications transmitting side with high speed, low hardware area, and superior efficiency. Paired with Tannera’s 5G NR LDPC Decoder IP Core, it is an optimal solution for channel coding in all 5G NR applications. The core supports ASIC and FPGA implementations.

Efficiency

at its peak

carefully designed to boost throughput and hardware usage efficiency,

provides the lowest power/energy consumption per encoded bit

The optimal solution

for all use cases

high bandwidth systems for the highest spectral efficiency,

low-power systems running on a reduced hardware footprint,

anything in between

Support for all codes defined in 5G NR standard (3GPP TS 38.212)
Coded throughput up to 39.2 Gb/s
Latency < 1 µs for all codes

AXI4-Stream interfaces for data transmission for easy integration
Extremely high hardware usage efficiency
Easily customizable as per request by the customer
Includes filler bit insertion, puncturing and filler bit removal

Implementation & performance results for Xilinx Ultrascale+ FPGA:

Clock	LUTs	FFs	BRAMs	Peak Info Throughput	Peak Efficiency
400 MHz	14,091	12,638	7.5	35.9 Gbps	2.55 Gbps/kLUT

Clock	LUTs	FFs	BRAMs	Peak Info Throughput	Peak Efficiency
400 MHz	14,091	12,638	7.5	35.9 Gbps	2.55 Gbps/kLUT

5G introduces a wide spectrum of applications that require high throughput, low latency, and ultra reliable channel coding while supporting very high flexibility. LDPC* codes are recognized as a solution for those challenges. At the transmitting side, the Tannera’s 5G NR LDPC Encoder IP Core is used to encode information sequences of bits into a protected codeword, which can be reconstructed at the receiving side even after the imperfect transmission through a telecommunication channel.

Tannera’s 5G NR LDPC Encoder IP Core optimizes all performance parameters (throughput, latency, flexibility, power) for the lowest possible amount of hardware resources (logic, memory, registers). As with every Tannera’s IP core, the hardware architecture is carefully designed to utilize hardware resources at their highest capacity in order to obtain the maximized hardware efficiency and maximized energy efficiency expressed as the number of decoded bits per joule.

As error correction control is almost always the most complex functionality of the entire physical layer (layer 1 - L1) baseband processing, Tannera’s 5G NR LDPC Encoder IP Core paired with Tannera’s 5G NR LDPC Decoder IP Core represents an optimal solution for this application.

*LDPC codes are the most frequently adopted channel codes in the entire telecommunication industry due to their superior error correcting performance and reasonable decoding complexity.

Use cases:

eMBB

eMBB (Enhanced Mobile Broadband) applications require the huge network capacity which states a challenge for a successful decoding in the RAN infrastructure both in computing resources and in power consumption. On the other hand, user equipment (UE) devices should support newly adopted speeds while remaining power efficient.

mMTC

mMTC (Massive Machine-Type Communications) are used to connect a large number of devices (machines) in order to enable a transformation of IoT. To support such a connectivity (over a million devices (users) per 1 square kilometer), a significant number of small-cell base stations must be placed at the small area. These stations must adeptly handle data from low-bandwidth devices, with the primary challenge residing not in the bandwidth but in the staggering volume of connections. It is imperative to integrate low-latency LDPC decoding, easily configurable for diverse device specifications. Moreover, the decoding process should demonstrate low power consumption and robust capability in managing an extensive array of connected devices.

URLLC

URLLC (Ultra Reliable Low Latency Communications) applications require ultra reliable and low latency solutions. Such a system does not allow retransmissions for reliability improvements (available in eMBB applications) since retransmissions require time, so low latency requests would not be met. A good example is autonomous driving, where it is expected to transfer a large amount of data, accurately, and with low latency. LDPC decoder built specifically for eMBB scenarios might not be able to provide the required reliability (99.999%) due to possible error floors. Tannera’s 5G NR LDPC Decoder IP Core provides low error-floor performance while keeping the waterfall region SNR low. (more about URLLC use cases available at the link)

Optical

Optical communications increasingly use 5G NR LDPC codes for channel coding. Some applications are standardized such as SDA OCT V 3.0 for free space optical communications (FSO). Tannera provides an optimized IP core that utilizes all the main features of 5G NR LDPC Decoder IP Core but with optimized hardware resources and power efficiency.

PRODUCTS >> FEC & DSP IP cores >> 5G NR FEC IP cores