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5G NR LDPC Decoder IP Core
Market-leading throughput and hardware usage efficiency with minimal power/energy consumption
Tannera’s 5G NR LDPC Decoder IP Core corrects bit errors that happen due to the imperfect transmission through a telecommunication channel. The core optimizes all performance parameters (throughput, latency, flexibility, SNR, power) for the lowest possible amount of hardware resources (logic, memory, registers). Such a feature is obtained by exploiting proprietary and patented LDPC decoding technology that maximizes the computing power by keeping hardware resources fully utilized. Therefore, Tannera’s 5G NR LDPC Decoder IP Core brings down the decoding complexity and enables efficient, reliable and high speed communications. The core supports ASIC and FPGA implementations.
Efficiency gain of 65%-100%
comparing to other market solutions
boosts throughput and hardware usage efficiency with up to 5.5 Gbps of information throughput and efficiency of over 73 Mbps/kLUT,
provides the lowest power/energy consumption per decoded bit
The optimal solution
for all use cases
high bandwidth systems for the highest spectral efficiency,
low-power systems running on a reduced hardware footprint,
anything in between
Support for all codes defined in 5G NR standard (3GPP TS 38.212)
Coded throughput up to 6.04 Gb/s
Information throughput up to 5.51 Gb/s
Latency < 10 µs for all codes
AXI4-Stream interfaces for easy integration
Extremely high hardware usage efficiency: the highest throughput for the limited hardware resources available on the market
Fast convergence due to a proprietary layered LDPC decoding algorithm
Stop criterion when all parity checks are satisfied for significant energy savings
Configurable LDPC decoding iterations number for speed/error correcting performance trade-off
Parallelism choice for optimal relation of throughput, latency, and resources
Includes de-puncturing and filler bit removal
Easily customizable as per request by the customer
Implementation & performance results for Xilinx Ultrascale+ FPGA for the highest parallelism:
Information throughput efficiency vs. code rate for 5G NR Base Graph 1 & Base Graph 2 codes for the highest parallelism:
5G introduces a wide spectrum of applications that require high throughput, low latency, and ultra reliable LDPC* decoding while supporting very high flexibility. This implies that the decoding requires extremely high computational power. Tannera’s 5G NR LDPC Decoder IP Core squeezes out the maximum computing power from available hardware resources.
Tannera’s 5G NR LDPC Decoder optimizes all performance parameters (throughput, latency, flexibility, SNR) for the lowest possible amount of hardware resources (logic, memory, registers). Such a feature is obtained by exploiting proprietary LDPC decoding algorithms and hardware architecture that maximizes the computing power by keeping hardware resources fully utilized. Therefore, Tannera’s 5G NR LDPC decoder decodes a maximum number of bits per unit of time and thus obtains the maximized energy efficiency expressed as the number of decoded bits per joule.
Tannera’s 5G NR LDPC Decoder IP Core corrects bit errors that happen due to the imperfect transmission through a telecommunication channel. Channel coding is almost always the most complex functionality of the entire physical layer (layer 1 - L1) baseband processing. Therefore, the complexity of the entire 5G NR data path L1 processing might be determined by the complexity of the LDPC decoder. Tannera’s 5G NR LDPC Decoder IP Core brings down that complexity and enables efficient, reliable and high throughput communications. The core supports ASIC and FPGA implementations.
*LDPC codes are the most frequently adopted channel codes in the entire telecommunication industry due to their superior error correcting performance and reasonable decoding complexity.