PRODUCTS >> FEC & DSP IP cores >> DVB-S2(X) FEC IP cores
DVB-S2(X) Decoder IP Core
Market-leading throughput and hardware usage efficiency with minimal power/energy consumption
Tannera’s DVB-S2(X) Decoder IP Core corrects bit errors that happen due to the imperfect transmission through a telecommunication channel using LDPC and BCH error correcting codes. The core optimizes all performance parameters (throughput, latency, SNR, power) for the lowest possible amount of hardware resources (logic, memory, registers). Such a feature is obtained by exploiting proprietary and patented LDPC decoding technology that maximizes the computing power by keeping hardware resources fully utilized. Therefore, Tannera’s DVB-S2(X) Decoder IP Core brings down the decoding complexity and enables efficient, reliable and high speed communications. The core supports ASIC and FPGA implementations.
Efficiency
at its peak
boosts throughput and hardware usage efficiency,
takes 250% less memory per decoded bit than other market solutions,
provides the lowest power/energy consumption per decoded bit
The optimal solution
for all use cases
high bandwidth systems for the highest spectral efficiency,
low-power systems running on a reduced hardware footprint,
anything in between
Support for all codes defined in DVB-S2 and DVB-S2X standards (ETSI EN 302 307-1 and ETSI EN 302 307-2)
Coded throughput up to 5.04 Gb/s at 10 decoding iterations
Information throughput up to 4.28 Gb/s
Latency < 50 µs for all codes
AXI4-Stream interfaces for easy integration
Superior hardware usage efficiency on the market: the highest throughput for the limited hardware resources
Fast convergence due to a proprietary layered LDPC decoding algorithm
Stop criterion when all parity checks are satisfied for significant energy savings
Configurable LDPC decoding iterations number for speed/error correcting performance trade-off
Easily customizable as per request by the customer
Implementation & performance results for Xilinx Ultrascale+ FPGA:
DVB-S2 and DVB-S2X standards address multiple satellite communication applications starting from S2 core application areas such as digital video broadcasting, forward link for interactive services using ACM (adaptive coding and modulation), video point-to-point links, internet trunking links, to S2X expansions to markets such as airborne (business jets), maritime, civil aviation internet access, VSAT terminals at higher frequency ranges or in tropical zones, small portable terminals for journalists and other professionals.
Such applications require ultra reliable, high throughput and/or high hardware efficiency FEC solutions. In the standard, LDPC codes are selected for majority of error protection with the supporting outer BCH code for correcting the remaining bit errors and providing high reliability (frame error rates of < 10−5). This implies that the decoding requires either high computational power or low hardware resources utilization. Tannera’s DVB-S2(X) Decoder IP Core squeezes out the maximum computing power from available hardware resources, hence it achieves the best hardware usage efficiency.
Tannera’s DVB-S2(X) Decoder IP Core optimizes all performance parameters (throughput, latency, flexibility, SNR) for the lowest possible amount of hardware resources (logic, memory, registers). Such a feature is obtained by exploiting proprietary LDPC decoding algorithms and hardware architecture that maximizes the computing power by keeping hardware resources fully utilized. Therefore, Tannera’s DVB-S2(X) Decoder IP Core decodes a maximum number of bits per unit of time and thus obtains the maximized energy efficiency expressed as the number of decoded bits per joule.