PRODUCTS >> FEC & DSP IP cores >> DVB-S2(X) FEC IP cores
DVB-S2(X) Encoder IP Core
High-speed, resource and energy efficient BCH+LDPC encoding solution.
Tannera’s DVB-S2(X) Encoder IP Core encodes the information bit sequences at the communications transmitting side with high speed, low hardware area, and superior efficiency. The core implements all DVB-S2 and DVB-S2X standard defined BCH (Bose–Chaudhuri–Hocquenghem) and LDPC (Low-Density Parity-Check) codes. Paired with Tannera’s DVB-S2(X) Decoder IP Core, it is an optimal solution for channel coding in all DVB-S2(X) applications. The core supports ASIC and FPGA implementations.
High speed
carefully designed to boost throughput at low hardware area
Flexible and customizable
high bandwidth systems for the highest spectral efficiency,
high throughput or low resources,
easy integration customizable per request
Support for all codes defined in DVB-S2 and DVB-S2X standards (ETSI EN 302 307-1 and ETSI EN 302 307-2)
Coded throughput up to 12.8 Gb/s (limited by the interface)
AXI4-Stream interfaces for data transmission for easy integration
Programmable interface bit width
High hardware usage efficiency
Easily customizable as per request by customer
Tannera’s DVB-S2(X) Encoder IP Core is a high-speed BCH+LDPC encoding solution for DVB-S2 and DVB-S2X standards. It is a standalone IP core or a supplementary IP Core to Tannera’s DVB-S2(X) Decoder IP Core with which it is an optimal solution for the highest spectral efficiency of the high bandwidth systems, as well as for the low power systems running on reduced hardware footprint.
DVB-S2 and DVB-S2X standards address multiple satellite communication applications starting from S2 core application areas such as digital video broadcasting, forward link for interactive services using ACM (adaptive coding and modulation), video point-to-point links, internet trunking links, to S2X expansions to markets such as airborne (business jets), maritime, civil aviation internet access, VSAT terminals at higher frequency ranges or in tropical zones, small portable terminals for journalists and other professionals.
Such applications require ultra reliable, high throughput and/or high hardware efficiency FEC solutions. In the standard LDPC codes are selected for majority of error protection with the supporting outer BCH code for correcting the remaining bit errors and providing high reliability (frame error rates of < 10−5).
Tannera’s DVB-S2X Encoder optimizes all performance parameters (throughput, latency, flexibility) for the lowest possible amount of hardware resources (logic, memory, registers). As with every Tannera’s IP core, the hardware architecture is carefully designed to utilize hardware resources at their highest capacity in order to obtain the maximized hardware efficiency and maximized energy efficiency expressed as the number of decoded bits per joule.
Through the analysis of error correcting performance of most commonly used decoding algorithms for 5G NR LDPC codes and their hardware complexity this paper aims to recommend optimal decoding algorithm and bit-widths for best ratio of error correcting performance to hardware resources used.
Analysis has shown that OMS algorithm has better error correcting performance than NMS algorithm, its optimal parameter choice is more robust with code rate variation, and has higher tolerance for calculations using low bit-width data.